(1) Field of the Invention
The present invention relates to a semiconductor device, and in particular to a potential generating circuit, a potential generating device, and a semiconductor device using the same, and a driving method thereof, all of which can provide an electric potential different from a supply voltage.
(2) Description Of Related Art
In recent years, increasingly finer LSIs have been produced. According to a scaling law, a modern MOS transistor has an ultrathin oxide film as a gate insulating film and thus, a supply voltage must be kept low in order to reduce leak current and to maintain and improve reliability. According to a design rule which specifies a minimum gate length of 0.13 [xcexcm], the oxide film thickness is 1.5 to 1.9 [nm] and the supply voltage is 1.2 to 1.5 [V]. On the other hand, a higher driving force must be provided for the MOS transistor to make a faster circuit and thus a threshold voltage must be reduced. However, a simply reduced threshold voltage may increase the leak current from the MOS transistor on standby.
To solve this problem, several methods of reducing off-leak current have been proposed, e.g., a method of causing the substrate of the MOS transistor on standby to have a negative potential and thus raising the threshold voltage of the MOS transistor. However, it is desirable that a single power supply should be used rather than a plurality of power supplies with different output voltages, since the latter may decrease the degree of circuit integration, lead to a cost increase, or reduce the efficiency. A typical prior art to solve this problem is a charge pump circuit which produces a negative voltage or a raised voltage from a supply voltage.
A substrate bias generating circuit using a prior charge pump circuit pumps up an electric charge out of an output terminal 67, for example, by causing N-channel MOS transistors 63 and 65 to periodically alternate between the ON state and the OFF state, respectively, as shown in FIG. 12. This allows the output terminal 67 to become a negative potential. FIGS. 13(a), 13(b), and 13(c) show how the potential xcfx86xe2x80x2 at an input terminal 61, the potential Vcpxe2x80x2 at an intermediate node 64, and the potential Vbbxe2x80x2 at the output terminal 67 vary with time, respectively.
With reference to FIG. 13, the operation of the prior substrate bias generating circuit will be described below. A pulse signal xcfx86xe2x80x2 with a voltage amplitude of supply potential (Vdd) is applied to the input terminal 61 as shown in FIG. 13(a). When the pulse signal xcfx86xe2x80x2 rises from the ground potential (0) to the supply potential (Vdd), the potential Vcpxe2x80x2at the intermediate node 64 rises from an initial value of xe2x88x92Vtn2, as shown in FIG. 13(b), via a charge pump capacitor 62. The value Vtn2 indicates the threshold voltage of the N-channel MOS transistor 65. The potential Vcpxe2x80x2 at the intermediate node 64 rises from the initial value of xe2x88x92Vtn2 by the value Vdd. When the potential Vcpxe2x80x2 at the intermediate node 64 rises to the potential (xe2x88x92Vtn2+Vdd), the N-channel MOS transistor 63 enters the ON state because of an increased gate voltage. This allows the charge pump capacitor 62 to slowly discharge electric charges accumulated in it, while the potential Vcpxe2x80x2 at the intermediate node 64 falls to the threshold voltage Vtn1 of the N-channel transistor 63. When the pulse signal xcfx86xe2x80x2 falls from the supply potential to the ground potential, the potential Vcpxe2x80x2 at the intermediate node 64 falls from an initial value of Vtn1 by the value Vdd. Then, the N-channel MOS transistor 65 enters the ON state, electric charges are accumulated in the charge pump capacitor 62, and the potential Vcpxe2x80x2 at the intermediate node 64 rises from an initial value of (Vtn1xe2x88x92Vdd) to the value xe2x88x92Vtn2. In this way, while the N-channel MOS transistor 63 is in the ON state and the N-channel MOS transistor 65 is in the OFF state, electric charges accumulated in the charge pump capacitor 62 are discharged to a grounding terminal, and on the contrary, while the N-channel MOS transistor 63 is in the OFF state and the N-channel MOS transistor 65 is in the ON state, electric charges incoming from the output terminal 67 are accumulated in the charge pump capacitor 62. The above-described operations are repeated to allow the potential Vbbxe2x80x2 at the output terminal 67 to slowly fall as shown in FIG. 13(c). The finally resultant voltage Vbbxe2x80x2 is expressed by Equation 1 below:
Vbbxe2x80x2=xe2x88x92Vdd+(Vtn1+Vtn2)xe2x80x83xe2x80x83(Equation 1)
As described above, if a pulse signal is applied to the input terminal 61, a negative potential is provided by the charge pump circuit to the output terminal 67. However, as seen from Equation 1, there is a problem that the absolute value of an output voltage from the prior substrate bias generating circuit may decrease by the sum of the threshold voltages of the N-channel MOS transistors 63 and 65. Furthermore, it is also a problem that the power efficiency may be as low as approximately 30%.
In order to solve the above-described problems, it is an object of the present invention to provide a potential generating circuit, a potential generating device, and a semiconductor device using the same, and a driving method thereof, all of which can produce no voltage drop in an output voltage.
A first potential generating circuit according to the present invention which can attain the above object comprises: a first capacitor; a second capacitor which is a ferroelectric capacitor connected in series to the first capacitor; an output terminal; a third capacitor for grounding the output terminal; a first switch for connecting a connecting node between the first capacitor and the second capacitor to the output terminal; and a second switch for connecting the connecting node to the ground; wherein during a first period, with the first switch and the second switch placed in the OFF state, a first terminal of the first capacitor opposed to the connecting node is provided with a positive potential and a second terminal of the second capacitor opposed to the connecting node is grounded; wherein during a second period following the first period, the first terminal is grounded and the first switch is placed in the ON state; wherein during a third period following the second period, the first switch is placed in the OFF state, the second switch is placed in the ON state, and the second terminal is provided with a positive potential; wherein during a fourth period following the third period, the second terminal is grounded; and wherein the first through fourth periods are repeated.
A first method of driving a potential generating circuit according to the present invention which can attain the above object comprises: in the above-described first potential generating circuit according to the present invention, a first period during which the first terminal is caused to have a positive potential, the second terminal is grounded, and the first switch and the second switch are placed in the OFF state; a second period following the first period, during which the first terminal is grounded and the first switch is placed in the ON state; a third period following the second period, during which the first switch is placed in the OFF state, the second switch is placed in the ON state, and the second terminal is caused to have a positive potential; and a fourth period following the third period, during which the second terminal is grounded; wherein the first through fourth periods are repeated.
A first potential generating device according to the present invention which can attain the above object comprises: the above-described first potential generating circuit according to the present invention; a control circuit for supplying to the potential generating circuit a driving signal for causing the first terminal to have a positive potential and grounding the second terminal, then grounding the first terminal and placing the first switch in the ON state, then placing the first switch and the second switch in the OFF and ON states, respectively, and causing the second terminal to have a positive potential, and then grounding the second terminal; and a potential detecting circuit for detecting an output potential at the output terminal; wherein the potential detecting circuit provides the control circuit with a control signal according to the detected output potential; and wherein the control circuit provides or stops providing the driving signal in response to the control signal.
A first method of driving a potential generating device according to the present invention which can attain the above object is a method of driving a potential generating device which comprises the above-described first potential generating circuit according to the present invention, a control circuit for supplying a driving signal to the potential generating circuit, and a potential detecting circuit for supplying a control signal to the control circuit, and comprises: a detecting step wherein the potential detecting circuit detects an output potential at the output terminal in the potential generating circuit; an enabling step wherein the potential detecting circuit provides the control circuit with an enabling signal so that the control circuit can provide the driving signal when the absolute value of the detected output potential is equal to or less than a first value, and the potential detecting circuit continues to provide the enabling signal until the absolute value is equal to or more than a second value; a disabling step wherein the potential detecting circuit provides the control circuit with a stop signal so that the control circuit can stop providing the driving signal when the absolute value is equal to or more than the second value, and the potential detecting circuit continues to provide the stop signal until the absolute value is equal to or less than the first value; a driving step wherein the control circuit provides the potential generating circuit with the driving signal upon receipt of the enabling signal; and a stopping step wherein the control circuit stops providing the potential generating circuit with the driving signal upon receipt of the stop signal.
A second potential generating device according to the present invention which can attain the above object comprises: the above-described first potential generating circuit according to the present invention; a control circuit for supplying to the potential generating circuit a driving signal for causing the first terminal to have a positive potential and grounding the second terminal, then grounding the first terminal and placing the first switch in the ON state, then placing the first switch and the second switch in the OFF and ON states, respectively, and causing the second terminal to have a positive potential, and then grounding the second terminal; and a potential detecting circuit for detecting an output potential at the output terminal; wherein the potential detecting circuit provides a predetermined signal when the absolute value of the detected output potential at the output terminal is equal to or less than a predetermined value; and wherein the control circuit provides a driving signal for supplying a positive potential to the first terminal, supplying a ground potential to the second terminal, and supplying such a potential that the first switch and the second switch are placed in the OFF state, when the control circuit receives the predetermined signal while providing the driving signal for supplying a ground potential to the first terminal and the second terminal and supplying such potentials that the first switch is placed in the OFF state and the second switch is placed in the ON state.
A third potential generating device according to the present invention which can attain the above object comprises: the above-described first potential generating circuit according to the present invention; a second potential generating circuit configured to comprise a fourth capacitor, a fifth capacitor which is a ferroelectric capacitor connected in series to the fourth capacitor, a sixth capacitor for grounding the output terminal, a third switch for connecting a second connecting node between the fourth capacitor and the fifth capacitor to the output terminal, and a fourth switch for connecting the second connecting node to the ground; a first control circuit for supplying to the first potential generating circuit according to the present invention a first driving signal for causing the first terminal to have a positive potential and grounding the second terminal, then grounding the first terminal and placing the first switch in the ON state, then placing the first switch and the second switch in the OFF and ON states, respectively, and causing the second terminal to have a positive potential, and then grounding the second terminal; a second control circuit for supplying to the second potential generating circuit a second driving signal for causing the third terminal of the fourth capacitor opposed to the second connecting node to have a positive potential and grounding the fourth terminal of the fifth capacitor opposed to the second connecting node, then grounding the third terminal and placing the third switch in the ON state, then placing the third switch and the fourth switch in the OFF and ON states, respectively, and causing the fourth terminal to have a positive potential, and then grounding the fourth terminal; and a potential detecting circuit for detecting an output potential at the output terminal; wherein an output timing of the first driving signal is shifted from an output timing of the second driving signal by a half cycle; wherein the potential detecting circuit provides the first control circuit and the second control circuit with a control signal according to the detected output potential; wherein the first control circuit provides or stops providing the first driving signal in response to the control signal; and wherein the second control circuit provides or stops providing the second driving signal in response to the control signal.
A second method of driving a potential generating device according to the present invention which can attain the above object is a method of driving the above-described third potential generating device according to the present invention, and comprises: a detecting step wherein the potential detecting circuit detects an output potential at the output terminal; an enabling step wherein the potential detecting circuit provides the first control circuit and the second control circuit with an enabling signal so that the control circuits can provide the first driving signal and the second driving signal when the absolute value of the detected output potential is equal to or less than a first value, and the potential detecting circuit continues to provide the enabling signal until the absolute value is equal to or more than a second value; a disabling step wherein the potential detecting circuit provides the first control circuit and the second control circuit with a stop signal so that the control circuits can stop providing the first driving signal and the second driving signal when the absolute value is equal to or more than the second value, and the potential detecting circuit continues to provide the stop signal until the absolute value is equal to or less than the first value; a first driving step wherein the first control circuit provides the first potential generating circuit according to the present invention with the first driving signal upon receipt of the enabling signal; a first stopping step wherein the first control circuit stops providing the first potential generating circuit according to the present invention with the first driving signal upon receipt of the stop signal; a second driving step wherein the second control circuit provides the second potential generating circuit according to the present invention with the second driving signal, at a timing shifted by a half cycle from the output timing of the first driving signal, upon receipt of the enabling signal; and a second stopping step wherein the second control circuit stops providing the second potential generating circuit with the second driving signal upon receipt of the stop signal.
A first semiconductor device according to the present invention which can attain the above object comprises: a memory cell; a fifth switch; and the above-described first potential generating device according to the present invention which is connected to a word line of the memory cell via the fifth switch; wherein the fifth switch is placed in the ON state while the memory cell is on standby.
A second semiconductor device according to the present invention which can attain the above object comprises: the above-described first potential generating device according to the present invention; a N-channel field-effect transistor; and a sixth switch for connecting the output terminal of the potential generating device to the substrate of the N-channel field-effect transistor; wherein the sixth switch is placed in the ON state while the N-channel field-effect transistor is on standby.
A third semiconductor device according to the present invention which can attain the above object comprises: the above-described first potential generating device according to the present invention; a logic circuit composed of field-effect transistors; a high-threshold P-channel field-effect transistor connecting the logic circuit to a predetermined potential and having a threshold voltage larger than those of the field-effect transistors; and a seventh switch for connecting the gate of the high-threshold P-channel field-effect transistor to the potential generating device; wherein the seventh switch is placed in the ON state while the logic circuit is in operation and in the OFF state while the logic circuit is on standby.
A fourth semiconductor device according to the present invention which can attain the above object comprises: the above-described first potential generating device according to the present invention; a logic circuit composed of field-effect transistors; a high-threshold N-channel field-effect transistor connecting the logic circuit to a predetermined potential and having a threshold voltage larger than those of the field-effect transistors; and an eighth switch for connecting the gate of the high-threshold N-channel field-effect transistor to the potential generating device; wherein the eighth switch is placed in the ON state while the logic circuit is on standby and in the OFF state while the logic circuit is in operation.
A first method of driving a semiconductor device according to the present invention which can attain the above object is a method of driving the above-described third semiconductor device according to the present invention, and comprises: an operating step wherein while the logic circuit is in operation, the seventh switch is placed in the ON state and a negative potential is supplied by the potential generating device to the gate of the high-threshold P-channel field-effect transistor; and a standby step wherein while the logic circuit is on standby, the seventh switch is placed in the OFF state and a positive potential is supplied to the gate of the high-threshold P-channel field-effect transistor.
A second method of driving a semiconductor device according to the present invention which can attain the above object is a method of driving the above-described fourth semiconductor device according to the present invention, and comprises: a standby step wherein while the logic circuit is on standby, the eighth switch is placed in the ON state and a negative potential is supplied by the potential generating device to the gate of the high-threshold N-channel field-effect transistor; and an operating step wherein while the logic circuit is in operation, the eighth switch is placed in the OFF state and a positive potential is supplied to the gate of the high-threshold N-channel field-effect transistor.